Follow Engadget, on the first day of the IEDM conference in San Francisco (USA), the two companies announced a new design to stack transistors vertically on a chip. With current processors and SoCs (system-on-chips), the transistors lie flat on the surface of the silicon, then current flows from side to side. In contrast, vertical transport field-effect transistors (VTFETs) are perpendicular to each other and current flows vertically.
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IBM and Samsung are trying to overcome the 1 nm . barrier |
According to IBM and Samsung, this design has two advantages. First, it will allow them to bypass many performance limitations to extend Moore’s Law beyond IBM’s current nanoboard technology. More importantly, the design results in less wasted energy thanks to the larger current. They estimate VTFETs will result in chips that are twice as fast or use 85% less power than chips designed with FinFET transistors.
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IBM and Samsung claim this process will usher in a future of phones with weeks of battery life on a single charge. The technology can also perform certain energy-intensive tasks, including mining cryptocurrencies that are more energy efficient and have less impact on the environment.
IBM and Samsung have not said when there are plans to commercialize this design, there are currently several companies trying to overcome the 1 nm barrier. In July, Intel said it aims to finalize the design for angstrom-scale chips by 2024. The company plans to achieve the feat using the new “Intel 20A” manufacturing process and semi-volumn. RibbonFET guide.
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